// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-05-02
// File Name    : WRADDR_GEN_TOP.v
// Module Name  : wr_addr_gen_top
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-02    Macro           1.0                     Original
//  
// *********************************************************************************
module wr_addr_gen_top(
    input CLK,
    input RST_N,
    output reg WR_FIX_EN,
    output reg [12:0] WR_FIX_ADDR,
    output reg [35:0] WR_FIX_DATA,
    wraddr_st_bus.wraddr wr_st_0,
    wraddr_st_bus.wraddr wr_st_1,
    wraddr_st_bus.wraddr wr_st_2,
    wraddr_st_bus.wraddr wr_st_3,
    wraddr_srammux_bus.wraddr wr_srammux_0,
    wraddr_srammux_bus.wraddr wr_srammux_1,
    wraddr_srammux_bus.wraddr wr_srammux_2
);
logic [3:0] WR_FIX_SRAMNUM;
logic [4:0] SRAM_NUM0;
logic [4:0] SRAM_NUM1;
logic [4:0] SRAM_NUM2;
logic [4:0] SRAM_NUM3;
logic [12:0] SRAM_ADDR0;
logic [12:0] SRAM_ADDR1;
logic [12:0] SRAM_ADDR2;
logic [12:0] SRAM_ADDR3;
logic [0:0] sram_tag0;
logic [0:0] sram_tag1;
logic [0:0] sram_tag2;
logic [0:0] sram_tag3;
logic [0:0] VLD_O_0;
logic [0:0] VLD_O_1;
logic [0:0] VLD_O_2;
logic [0:0] VLD_O_3;
logic [4:0] SRAM_NUM_OUT_0;
logic [4:0] SRAM_NUM_OUT_1;
logic [4:0] SRAM_NUM_OUT_2;
logic [4:0] SRAM_NUM_OUT_3;
logic [12:0] SRAM_ADDR_O_0;
logic [12:0] SRAM_ADDR_O_1;
logic [12:0] SRAM_ADDR_O_2;
logic [12:0] SRAM_ADDR_O_3;
logic [35:0] DATA_O_0;
logic [35:0] DATA_O_1;
logic [35:0] DATA_O_2;
logic [35:0] DATA_O_3;
logic [0:0] SOP_O_0;
logic [0:0] SOP_O_1;
logic [0:0] SOP_O_2;
logic [0:0] SOP_O_3;
logic [0:0] EOP_O_0;
logic [0:0] EOP_O_1;
logic [0:0] EOP_O_2;
logic [0:0] EOP_O_3;

always@(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        sram_tag0<=1'b0;
        sram_tag1<=1'b0;
        sram_tag2<=1'b0;
        sram_tag3<=1'b0;
        WR_FIX_EN<=1'b0;
        WR_FIX_ADDR<=13'd0;
        WR_FIX_DATA<=36'd0;
        WR_FIX_SRAMNUM<=4'd0;
    end
    else if(VLD_O_0&&SRAM_NUM_OUT_0<16) begin
        sram_tag0<=1'b1;
        WR_FIX_EN<=VLD_O_0;
        WR_FIX_ADDR<=SRAM_ADDR_O_0;
        WR_FIX_DATA<=DATA_O_0;
        WR_FIX_SRAMNUM<=SRAM_NUM_OUT_0;
    end
    else if(VLD_O_1&&SRAM_NUM_OUT_1<16) begin
        sram_tag1<=1'b1;
        WR_FIX_EN<=VLD_O_1;
        WR_FIX_ADDR<=SRAM_ADDR_O_1;
        WR_FIX_DATA<=DATA_O_1;
        WR_FIX_SRAMNUM<=SRAM_NUM_OUT_1;
    end
    else if(VLD_O_2&&SRAM_NUM_OUT_2<16) begin
        sram_tag2<=1'b1;
        WR_FIX_EN<=VLD_O_2;
        WR_FIX_ADDR<=SRAM_ADDR_O_2;
        WR_FIX_DATA<=DATA_O_2;
        WR_FIX_SRAMNUM<=SRAM_NUM_OUT_2;
    end
    else if(VLD_O_3&&SRAM_NUM_OUT_3<16) begin
        sram_tag3<=1'b1;
        WR_FIX_EN<=VLD_O_3;
        WR_FIX_ADDR<=SRAM_ADDR_O_3;
        WR_FIX_DATA<=DATA_O_3;
        WR_FIX_SRAMNUM<=SRAM_NUM_OUT_3;
    end
    else begin
        sram_tag0<=1'b0;
        sram_tag1<=1'b0;
        sram_tag2<=1'b0;
        sram_tag3<=1'b0;
        WR_FIX_EN<=1'b0;
        WR_FIX_ADDR<=18'd0;
        WR_FIX_DATA<=36'd0;
        WR_FIX_SRAMNUM<=4'd0;
    end
end

always@(posedge CLK or negedge RST_N)begin
    if(!RST_N)begin
        wr_srammux_0.WR_EN<=1'b0;
        wr_srammux_0.WR_ADDR<=18'd0;
        wr_srammux_0.WR_DATA<=36'd0;
        wr_srammux_0.WR_SRAM_NUM<=5'd0;
        wr_srammux_1.WR_EN<=1'b0;
        wr_srammux_1.WR_ADDR<=18'd0;
        wr_srammux_1.WR_DATA<=36'd0;
        wr_srammux_1.WR_SRAM_NUM<=5'd0;
        wr_srammux_2.WR_EN<=1'b0;
        wr_srammux_2.WR_ADDR<=18'd0;
        wr_srammux_2.WR_DATA<=36'd0;
        wr_srammux_2.WR_SRAM_NUM<=5'd0;
    end
    else begin
        if((VLD_O_3&!sram_tag3)&(VLD_O_2&!sram_tag2)&(VLD_O_1&!sram_tag1))begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=VLD_O_2;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_1.WR_DATA<=DATA_O_2;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_2.WR_EN<=VLD_O_1;
            wr_srammux_2.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_2.WR_DATA<=DATA_O_1;
            wr_srammux_2.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
        end
        else if((VLD_O_3&!sram_tag3)&(VLD_O_2&!sram_tag2)&(VLD_O_0&!sram_tag0))begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=VLD_O_2;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_1.WR_DATA<=DATA_O_2;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_2.WR_EN<=VLD_O_0;
            wr_srammux_2.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_2.WR_DATA<=DATA_O_0;
            wr_srammux_2.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
        end
        else if((VLD_O_3&!sram_tag3)&(VLD_O_1&!sram_tag1)&(VLD_O_0&!sram_tag0))begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=VLD_O_1;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_1.WR_DATA<=DATA_O_1;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
            wr_srammux_2.WR_EN<=VLD_O_0;
            wr_srammux_2.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_2.WR_DATA<=DATA_O_0;
            wr_srammux_2.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
        end
        else if((VLD_O_2&!sram_tag2)&(VLD_O_1&!sram_tag1)&(VLD_O_0&!sram_tag0))begin
            wr_srammux_0.WR_EN<=VLD_O_2;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_0.WR_DATA<=DATA_O_2;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_1.WR_EN<=VLD_O_1;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_1.WR_DATA<=DATA_O_1;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
            wr_srammux_2.WR_EN<=VLD_O_0;
            wr_srammux_2.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_2.WR_DATA<=DATA_O_0;
            wr_srammux_2.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
        end
        else if((VLD_O_1&!sram_tag1)&(VLD_O_0&!sram_tag0))begin
            wr_srammux_0.WR_EN<=VLD_O_1;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_0.WR_DATA<=DATA_O_1;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
            wr_srammux_1.WR_EN<=VLD_O_0;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_1.WR_DATA<=DATA_O_0;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if((VLD_O_3&!sram_tag3)&(VLD_O_2&!sram_tag2))begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=VLD_O_2;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_1.WR_DATA<=DATA_O_2;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if((VLD_O_3&!sram_tag3)&(VLD_O_1&!sram_tag1))begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=VLD_O_1;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_1.WR_DATA<=DATA_O_1;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if((VLD_O_2&!sram_tag2)&(VLD_O_0&!sram_tag0))begin
            wr_srammux_0.WR_EN<=VLD_O_2;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_0.WR_DATA<=DATA_O_2;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_1.WR_EN<=VLD_O_0;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_1.WR_DATA<=DATA_O_0;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if((VLD_O_3&!sram_tag3)&(VLD_O_0&!sram_tag0))begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=VLD_O_0;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_1.WR_DATA<=DATA_O_0;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if((VLD_O_2&!sram_tag2)&(VLD_O_1&!sram_tag1))begin
            wr_srammux_0.WR_EN<=VLD_O_2;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_0.WR_DATA<=DATA_O_2;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_1.WR_EN<=VLD_O_1;
            wr_srammux_1.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_1.WR_DATA<=DATA_O_1;
            wr_srammux_1.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if(VLD_O_0&!sram_tag0)begin
            wr_srammux_0.WR_EN<=VLD_O_0;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_0;
            wr_srammux_0.WR_DATA<=DATA_O_0;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_0;
            wr_srammux_1.WR_EN<=1'b0;
            wr_srammux_1.WR_ADDR<=18'd0;
            wr_srammux_1.WR_DATA<=36'd0;
            wr_srammux_1.WR_SRAM_NUM<=5'd0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if(VLD_O_1&!sram_tag1)begin
            wr_srammux_0.WR_EN<=VLD_O_1;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_1;
            wr_srammux_0.WR_DATA<=DATA_O_1;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_1;
            wr_srammux_1.WR_EN<=1'b0;
            wr_srammux_1.WR_ADDR<=18'd0;
            wr_srammux_1.WR_DATA<=36'd0;
            wr_srammux_1.WR_SRAM_NUM<=5'd0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if(VLD_O_2&!sram_tag2)begin
            wr_srammux_0.WR_EN<=VLD_O_2;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_2;
            wr_srammux_0.WR_DATA<=DATA_O_2;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_2;
            wr_srammux_1.WR_EN<=1'b0;
            wr_srammux_1.WR_ADDR<=18'd0;
            wr_srammux_1.WR_DATA<=36'd0;
            wr_srammux_1.WR_SRAM_NUM<=5'd0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else if(VLD_O_3&!sram_tag3)begin
            wr_srammux_0.WR_EN<=VLD_O_3;
            wr_srammux_0.WR_ADDR<=SRAM_ADDR_O_3;
            wr_srammux_0.WR_DATA<=DATA_O_3;
            wr_srammux_0.WR_SRAM_NUM<=SRAM_NUM_OUT_3;
            wr_srammux_1.WR_EN<=1'b0;
            wr_srammux_1.WR_ADDR<=18'd0;
            wr_srammux_1.WR_DATA<=36'd0;
            wr_srammux_1.WR_SRAM_NUM<=5'd0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
        else begin
            wr_srammux_0.WR_EN<=1'b0;
            wr_srammux_0.WR_ADDR<=18'd0;
            wr_srammux_0.WR_DATA<=36'd0;
            wr_srammux_0.WR_SRAM_NUM<=5'd0;
            wr_srammux_1.WR_EN<=1'b0;
            wr_srammux_1.WR_ADDR<=18'd0;
            wr_srammux_1.WR_DATA<=36'd0;
            wr_srammux_1.WR_SRAM_NUM<=5'd0;
            wr_srammux_2.WR_EN<=1'b0;
            wr_srammux_2.WR_ADDR<=18'd0;
            wr_srammux_2.WR_DATA<=36'd0;
            wr_srammux_2.WR_SRAM_NUM<=5'd0;
        end
    end
end

wr_addr_decoder u_wr_addr_decoder0(
    .ADDR(wr_st_0.ADDR),
    .SRAM_NUM(SRAM_NUM0),
    .SRAM_ADDR(SRAM_ADDR0)
);
wr_addr_decoder u_wr_addr_decoder1(
    .ADDR(wr_st_1.ADDR),
    .SRAM_NUM(SRAM_NUM1),
    .SRAM_ADDR(SRAM_ADDR1)
);
wr_addr_decoder u_wr_addr_decoder2(
    .ADDR(wr_st_2.ADDR),
    .SRAM_NUM(SRAM_NUM2),
    .SRAM_ADDR(SRAM_ADDR2)
);
wr_addr_decoder u_wr_addr_decoder3(
    .ADDR(wr_st_3.ADDR),
    .SRAM_NUM(SRAM_NUM3),
    .SRAM_ADDR(SRAM_ADDR3)
);

ctrl u_ctrl0(
    .CLK(CLK),
    .RST_N(RST_N),
    .SRAM_NUM(SRAM_NUM0),
    .SOP(wr_st_0.SOP),
    .EOP(wr_st_0.EOP),
    .VLD(wr_st_0.VLD),
    .DATA(wr_st_0.DATA),
    .SRAM_ADDR(SRAM_ADDR0),
    .SRAM_NUM_O(SRAM_NUM_OUT_0),
    .SOP_O(SOP_O_0),
    .EOP_O(EOP_O_0),
    .VLD_O(VLD_O_0),
    .DATA_O(DATA_O_0),
    .SRAM_ADDR_O(SRAM_ADDR_O_0)
);
ctrl u_ctrl1(
    .CLK(CLK),
    .RST_N(RST_N),
    .SRAM_NUM(SRAM_NUM1),
    .SOP(wr_st_1.SOP),
    .EOP(wr_st_1.EOP),
    .VLD(wr_st_1.VLD),
    .DATA(wr_st_1.DATA),
    .SRAM_ADDR(SRAM_ADDR1),
    .SRAM_NUM_O(SRAM_NUM_OUT_1),
    .SOP_O(SOP_O_1),
    .EOP_O(EOP_O_1),
    .VLD_O(VLD_O_1),
    .DATA_O(DATA_O_1),
    .SRAM_ADDR_O(SRAM_ADDR_O_1)
);
ctrl u_ctrl2(
    .CLK(CLK),
    .RST_N(RST_N),
    .SRAM_NUM(SRAM_NUM2),
    .SOP(wr_st_2.SOP),
    .EOP(wr_st_2.EOP),
    .VLD(wr_st_2.VLD),
    .DATA(wr_st_2.DATA),
    .SRAM_ADDR(SRAM_ADDR2),
    .SRAM_NUM_O(SRAM_NUM_OUT_2),
    .SOP_O(SOP_O_2),
    .EOP_O(EOP_O_2),
    .VLD_O(VLD_O_2),
    .DATA_O(DATA_O_2),
    .SRAM_ADDR_O(SRAM_ADDR_O_2)
);
ctrl u_ctrl3(
    .CLK(CLK),
    .RST_N(RST_N),
    .SRAM_NUM(SRAM_NUM3),
    .SOP(wr_st_3.SOP),
    .EOP(wr_st_3.EOP),
    .VLD(wr_st_3.VLD),
    .DATA(wr_st_3.DATA),
    .SRAM_ADDR(SRAM_ADDR3),
    .SRAM_NUM_O(SRAM_NUM_OUT_3),
    .SOP_O(SOP_O_3),
    .EOP_O(EOP_O_3),
    .VLD_O(VLD_O_3),
    .DATA_O(DATA_O_3),
    .SRAM_ADDR_O(SRAM_ADDR_O_3)
);

endmodule
